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Shader_Ir: Change Debug Asserts for Log Warnings
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5a06e33859
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3 changed files with 17 additions and 10 deletions
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@ -42,11 +42,14 @@ u32 ShaderIR::DecodeArithmetic(NodeBlock& bb, u32 pc) {
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
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DEBUG_ASSERT_MSG(instr.fmul.tab5cb8_2 == 0, "FMUL tab5cb8_2({}) is not implemented",
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instr.fmul.tab5cb8_2.Value());
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DEBUG_ASSERT_MSG(
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instr.fmul.tab5c68_0 == 1, "FMUL tab5cb8_0({}) is not implemented",
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instr.fmul.tab5c68_0.Value()); // SMO typical sends 1 here which seems to be the default
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if (instr.fmul.tab5cb8_2 != 0) {
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LOG_WARNING(HW_GPU, "FMUL tab5cb8_2({}) is not implemented",
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instr.fmul.tab5cb8_2.Value());
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}
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if (instr.fmul.tab5c68_0 != 1) {
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LOG_WARNING(HW_GPU, "FMUL tab5cb8_0({}) is not implemented",
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instr.fmul.tab5c68_0.Value());
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}
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op_b = GetOperandAbsNegFloat(op_b, false, instr.fmul.negate_b);
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