[dynarmic] revert memory imm precalc

This commit is contained in:
lizzie 2025-07-22 05:03:15 +01:00
parent 1babfd5812
commit 9917479e60

View file

@ -58,51 +58,46 @@ static bool SharedDecodeAndOperation(TranslatorVisitor& v, bool wback, IR::MemOp
address = v.X(64, Rn); address = v.X(64, Rn);
} }
IR::U64 offs = v.ir.Imm64(0);
if (replicate) { if (replicate) {
// CPU likes when we read first and then we do operations; Sure, OOO, but might as well for (size_t s = 0; s < selem; s++) {
IR::UAnyU128 p_elements[4] = {}; //max upper bound=4 elements
for (size_t s = 0; s < selem; ++s) {
p_elements[s] = v.Mem(v.ir.Add(address, v.ir.Imm64(ebytes * s)), ebytes, IR::AccType::VEC);
}
// schedule ops after
for (size_t s = 0; s < selem; ++s) {
const Vec tt = static_cast<Vec>((VecNumber(Vt) + s) % 32); const Vec tt = static_cast<Vec>((VecNumber(Vt) + s) % 32);
const IR::U128 broadcasted_element = v.ir.VectorBroadcast(esize, p_elements[s]); const IR::UAnyU128 element = v.Mem(v.ir.Add(address, offs), ebytes, IR::AccType::VEC);
const IR::U128 broadcasted_element = v.ir.VectorBroadcast(esize, element);
v.V(datasize, tt, broadcasted_element); v.V(datasize, tt, broadcasted_element);
offs = v.ir.Add(offs, v.ir.Imm64(ebytes));
} }
} else { } else {
if (memop == IR::MemOp::LOAD) { for (size_t s = 0; s < selem; s++) {
IR::UAny p_elements[4] = {}; //max upper bound=4 elements const Vec tt = static_cast<Vec>((VecNumber(Vt) + s) % 32);
for (size_t s = 0; s < selem; ++s) { const IR::U128 rval = v.V(128, tt);
p_elements[s] = v.Mem(v.ir.Add(address, v.ir.Imm64(ebytes * s)), ebytes, IR::AccType::VEC);
} if (memop == IR::MemOp::LOAD) {
for (size_t s = 0; s < selem; ++s) { const IR::UAny elem = v.Mem(v.ir.Add(address, offs), ebytes, IR::AccType::VEC);
const Vec tt = static_cast<Vec>((VecNumber(Vt) + s) % 32); const IR::U128 vec = v.ir.VectorSetElement(esize, rval, index, elem);
const IR::U128 rval = v.V(128, tt);
const IR::U128 vec = v.ir.VectorSetElement(esize, rval, index, p_elements[s]);
v.V(128, tt, vec); v.V(128, tt, vec);
} } else {
} else {
for (size_t s = 0; s < selem; ++s) {
const Vec tt = static_cast<Vec>((VecNumber(Vt) + s) % 32);
const IR::U128 rval = v.V(128, tt);
const IR::UAny elem = v.ir.VectorGetElement(esize, rval, index); const IR::UAny elem = v.ir.VectorGetElement(esize, rval, index);
v.Mem(v.ir.Add(address, v.ir.Imm64(ebytes * s)), ebytes, IR::AccType::VEC, elem); v.Mem(v.ir.Add(address, offs), ebytes, IR::AccType::VEC, elem);
} }
offs = v.ir.Add(offs, v.ir.Imm64(ebytes));
} }
} }
IR::U64 offs = v.ir.Imm64(ebytes * selem);
if (wback) { if (wback) {
if (*Rm != Reg::SP) { if (*Rm != Reg::SP) {
offs = v.X(64, *Rm); offs = v.X(64, *Rm);
} }
if (Rn == Reg::SP) { if (Rn == Reg::SP) {
v.SP(64, v.ir.Add(address, offs)); v.SP(64, v.ir.Add(address, offs));
} else { } else {
v.X(64, Rn, v.ir.Add(address, offs)); v.X(64, Rn, v.ir.Add(address, offs));
} }
} }
return true; return true;
} }