From 5ddbef9c8a2c9c8d8ec4986e794b11651ec3d486 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Oct 2018 15:53:21 -0400 Subject: [PATCH 1/4] maxwell_dma: Remove unused variables in HandleCopy() These pointer variables are never used, so we can get rid of them. --- src/video_core/engines/maxwell_dma.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/video_core/engines/maxwell_dma.cpp b/src/video_core/engines/maxwell_dma.cpp index 103cd110eb..a945daf6a4 100644 --- a/src/video_core/engines/maxwell_dma.cpp +++ b/src/video_core/engines/maxwell_dma.cpp @@ -91,9 +91,6 @@ void MaxwellDMA::HandleCopy() { rasterizer.InvalidateRegion(dest_cpu, dst_size); }; - u8* src_buffer = Memory::GetPointer(source_cpu); - u8* dst_buffer = Memory::GetPointer(dest_cpu); - if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) { ASSERT(regs.src_params.size_z == 1); // If the input is tiled and the output is linear, deswizzle the input and copy it over. From 04e8b81de09265aa45b30e6f293d4c4d83eda006 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Oct 2018 15:54:43 -0400 Subject: [PATCH 2/4] maxwell_dma: Make FlushAndInvalidate's size parameter a u64 This prevents truncation warnings at the lambda's usage sites. --- src/video_core/engines/maxwell_dma.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/video_core/engines/maxwell_dma.cpp b/src/video_core/engines/maxwell_dma.cpp index a945daf6a4..a2157fa294 100644 --- a/src/video_core/engines/maxwell_dma.cpp +++ b/src/video_core/engines/maxwell_dma.cpp @@ -80,7 +80,7 @@ void MaxwellDMA::HandleCopy() { std::size_t copy_size = regs.x_count * regs.y_count; - const auto FlushAndInvalidate = [&](u32 src_size, u32 dst_size) { + const auto FlushAndInvalidate = [&](u32 src_size, u64 dst_size) { // TODO(Subv): For now, manually flush the regions until we implement GPU-accelerated // copying. rasterizer.FlushRegion(source_cpu, src_size); From 92996ab8b33071f6381b675d59c4efca8a27c15c Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Oct 2018 15:55:58 -0400 Subject: [PATCH 3/4] maxwell_dma: Make variables const where applicable within HandleCopy() These are never modified, so we can make that assumption explicit. --- src/video_core/engines/maxwell_dma.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/video_core/engines/maxwell_dma.cpp b/src/video_core/engines/maxwell_dma.cpp index a2157fa294..9469bce596 100644 --- a/src/video_core/engines/maxwell_dma.cpp +++ b/src/video_core/engines/maxwell_dma.cpp @@ -78,7 +78,7 @@ void MaxwellDMA::HandleCopy() { ASSERT(regs.exec.enable_2d == 1); - std::size_t copy_size = regs.x_count * regs.y_count; + const std::size_t copy_size = regs.x_count * regs.y_count; const auto FlushAndInvalidate = [&](u32 src_size, u64 dst_size) { // TODO(Subv): For now, manually flush the regions until we implement GPU-accelerated @@ -95,7 +95,7 @@ void MaxwellDMA::HandleCopy() { ASSERT(regs.src_params.size_z == 1); // If the input is tiled and the output is linear, deswizzle the input and copy it over. - u32 src_bytes_per_pixel = regs.src_pitch / regs.src_params.size_x; + const u32 src_bytes_per_pixel = regs.src_pitch / regs.src_params.size_x; FlushAndInvalidate(regs.src_pitch * regs.src_params.size_y, copy_size * src_bytes_per_pixel); @@ -108,7 +108,7 @@ void MaxwellDMA::HandleCopy() { ASSERT(regs.dst_params.size_z == 1); ASSERT(regs.src_pitch == regs.x_count); - u32 src_bpp = regs.src_pitch / regs.x_count; + const u32 src_bpp = regs.src_pitch / regs.x_count; FlushAndInvalidate(regs.src_pitch * regs.y_count, regs.dst_params.size_x * regs.dst_params.size_y * src_bpp); From cdea084c7df85cae66535ed0313b433635ab3e64 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 20 Oct 2018 15:58:06 -0400 Subject: [PATCH 4/4] engines/maxwell_*: Use nested namespace specifiers where applicable These three source files are the only ones within the engines directory that don't use nested namespaces. We may as well change these over to keep things consistent. --- src/video_core/engines/maxwell_3d.cpp | 6 ++---- src/video_core/engines/maxwell_compute.cpp | 6 ++---- src/video_core/engines/maxwell_dma.cpp | 6 ++---- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index 8afd26fe90..bca014a4ac 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp @@ -13,8 +13,7 @@ #include "video_core/renderer_base.h" #include "video_core/textures/texture.h" -namespace Tegra { -namespace Engines { +namespace Tegra::Engines { /// First register id that is actually a Macro call. constexpr u32 MacroRegistersStart = 0xE00; @@ -408,5 +407,4 @@ void Maxwell3D::ProcessClearBuffers() { rasterizer.Clear(); } -} // namespace Engines -} // namespace Tegra +} // namespace Tegra::Engines diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp index 59e28b22d1..8b5f083519 100644 --- a/src/video_core/engines/maxwell_compute.cpp +++ b/src/video_core/engines/maxwell_compute.cpp @@ -6,8 +6,7 @@ #include "core/core.h" #include "video_core/engines/maxwell_compute.h" -namespace Tegra { -namespace Engines { +namespace Tegra::Engines { void MaxwellCompute::WriteReg(u32 method, u32 value) { ASSERT_MSG(method < Regs::NUM_REGS, @@ -26,5 +25,4 @@ void MaxwellCompute::WriteReg(u32 method, u32 value) { } } -} // namespace Engines -} // namespace Tegra +} // namespace Tegra::Engines diff --git a/src/video_core/engines/maxwell_dma.cpp b/src/video_core/engines/maxwell_dma.cpp index 9469bce596..b8a78cf827 100644 --- a/src/video_core/engines/maxwell_dma.cpp +++ b/src/video_core/engines/maxwell_dma.cpp @@ -7,8 +7,7 @@ #include "video_core/rasterizer_interface.h" #include "video_core/textures/decoders.h" -namespace Tegra { -namespace Engines { +namespace Tegra::Engines { MaxwellDMA::MaxwellDMA(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager) : memory_manager(memory_manager), rasterizer{rasterizer} {} @@ -119,5 +118,4 @@ void MaxwellDMA::HandleCopy() { } } -} // namespace Engines -} // namespace Tegra +} // namespace Tegra::Engines