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WIP: [vk] Enable line stipple and depth bound reg transfer
It should improve line stipple accuracy and the depth stencilling. Co-authored-by: crueter <crueter@eden-emu.dev> Signed-off-by: Aleksandr Popovich <popovich@eden-emu.dev>
This commit is contained in:
parent
2e092010e6
commit
ffea122af1
8 changed files with 44 additions and 12 deletions
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@ -86,6 +86,12 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d, DynamicFe
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alpha_to_one_enabled.Assign(regs.anti_alias_alpha_control.alpha_to_one != 0 ? 1 : 0);
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app_stage.Assign(maxwell3d.engine_state);
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depth_bounds_min = static_cast<u32>(regs.depth_bounds[0]);
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depth_bounds_max = static_cast<u32>(regs.depth_bounds[1]);
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line_stipple_factor = regs.line_stipple_params.factor;
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line_stipple_pattern = regs.line_stipple_params.pattern;
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for (size_t i = 0; i < regs.rt.size(); ++i) {
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color_formats[i] = static_cast<u8>(regs.rt[i].format);
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}
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@ -258,6 +264,8 @@ void FixedPipelineState::DynamicState::Refresh3(const Maxwell& regs) {
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Maxwell::ViewportClipControl::GeometryClip::FrustumXYZ ||
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regs.viewport_clip_control.geometry_clip ==
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Maxwell::ViewportClipControl::GeometryClip::FrustumZ);
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line_stipple_enable.Assign(regs.line_stipple_enable);
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}
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size_t FixedPipelineState::Hash() const noexcept {
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@ -150,6 +150,7 @@ struct FixedPipelineState {
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BitField<6, 4, u32> logic_op;
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BitField<10, 1, u32> logic_op_enable;
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BitField<11, 1, u32> depth_clamp_disabled;
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BitField<12, 1, u32> line_stipple_enable;
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};
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union {
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u32 raw2;
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@ -218,6 +219,7 @@ struct FixedPipelineState {
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u32 alpha_test_ref;
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u32 point_size;
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std::array<u16, Maxwell::NumViewports> viewport_swizzles;
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union {
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u64 attribute_types; // Used with VK_EXT_vertex_input_dynamic_state
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@ -233,6 +235,12 @@ struct FixedPipelineState {
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VideoCommon::TransformFeedbackState xfb_state;
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u32 depth_bounds_min;
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u32 depth_bounds_max;
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u32 line_stipple_factor;
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u32 line_stipple_pattern;
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void Refresh(Tegra::Engines::Maxwell3D& maxwell3d, DynamicFeatures& features);
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size_t Hash() const noexcept;
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@ -701,6 +701,7 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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.depthBiasClamp = 0.0f,
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.depthBiasSlopeFactor = 0.0f,
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.lineWidth = 1.0f,
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// TODO(alekpop): Transfer from regs
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};
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VkPipelineRasterizationLineStateCreateInfoEXT line_state{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT,
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@ -708,9 +709,9 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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.lineRasterizationMode = key.state.smooth_lines != 0
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? VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT
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: VK_LINE_RASTERIZATION_MODE_RECTANGULAR_EXT,
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.stippledLineEnable = VK_FALSE, // TODO
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.lineStippleFactor = 0,
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.lineStipplePattern = 0,
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.stippledLineEnable = dynamic.line_stipple_enable ? VK_TRUE : VK_FALSE,
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.lineStippleFactor = key.state.line_stipple_factor,
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.lineStipplePattern = static_cast<uint16_t>(key.state.line_stipple_pattern),
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};
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VkPipelineRasterizationConservativeStateCreateInfoEXT conservative_raster{
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.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT,
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@ -763,8 +764,8 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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.stencilTestEnable = dynamic.stencil_enable,
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.front = GetStencilFaceState(dynamic.front),
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.back = GetStencilFaceState(dynamic.back),
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.minDepthBounds = 0.0f,
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.maxDepthBounds = 0.0f,
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.minDepthBounds = static_cast<f32>(key.state.depth_bounds_min),
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.maxDepthBounds = static_cast<f32>(key.state.depth_bounds_max),
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};
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if (dynamic.depth_bounds_enable && !device.IsDepthBoundsSupported()) {
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LOG_WARNING(Render_Vulkan, "Depth bounds is enabled but not supported");
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@ -855,9 +856,6 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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VK_DYNAMIC_STATE_LOGIC_OP_ENABLE_EXT,
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// additional state3 extensions
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// FIXME(crueter): conservative rasterization is totally broken
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// VK_DYNAMIC_STATE_RASTERIZATION_SAMPLES_EXT,
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VK_DYNAMIC_STATE_LINE_RASTERIZATION_MODE_EXT,
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VK_DYNAMIC_STATE_CONSERVATIVE_RASTERIZATION_MODE_EXT,
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@ -865,7 +863,6 @@ void GraphicsPipeline::MakePipeline(VkRenderPass render_pass) {
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VK_DYNAMIC_STATE_LINE_STIPPLE_ENABLE_EXT,
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VK_DYNAMIC_STATE_ALPHA_TO_COVERAGE_ENABLE_EXT,
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VK_DYNAMIC_STATE_ALPHA_TO_ONE_ENABLE_EXT,
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VK_DYNAMIC_STATE_TESSELLATION_DOMAIN_ORIGIN_EXT,
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VK_DYNAMIC_STATE_DEPTH_CLIP_ENABLE_EXT,
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VK_DYNAMIC_STATE_PROVOKING_VERTEX_MODE_EXT,
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};
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@ -935,6 +935,7 @@ void RasterizerVulkan::UpdateDynamicStates() {
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UpdateDepthBounds(regs);
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UpdateStencilFaces(regs);
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UpdateLineWidth(regs);
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// UpdateLineStipple(regs); // TODO
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const u8 dynamic_state = Settings::values.dyna_state.GetValue();
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@ -1368,6 +1369,17 @@ void RasterizerVulkan::UpdateLineStippleEnable(Tegra::Engines::Maxwell3D::Regs&
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});
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}
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void RasterizerVulkan::UpdateLineStipple(Tegra::Engines::Maxwell3D::Regs& regs)
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{
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if (!state_tracker.TouchLineStippleEnable()) {
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return;
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}
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scheduler.Record([params = regs.line_stipple_params](vk::CommandBuffer cmdbuf) {
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cmdbuf.SetLineStippleEXT(params.factor, u16(params.pattern));
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});
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}
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void RasterizerVulkan::UpdateLineRasterizationMode(Tegra::Engines::Maxwell3D::Regs& regs)
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{
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// if (!state_tracker.TouchLi()) {
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@ -180,6 +180,7 @@ private:
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void UpdateRasterizerDiscardEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateConservativeRasterizationMode(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateLineStippleEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateLineStipple(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateLineRasterizationMode(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateDepthBiasEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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void UpdateLogicOpEnable(Tegra::Engines::Maxwell3D::Regs& regs);
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@ -52,9 +52,7 @@ Flags MakeInvalidationFlags() {
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VertexInput,
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StateEnable,
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PrimitiveRestartEnable,
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RasterizerDiscardEnable,
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ConservativeRasterizationMode,
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LineStippleEnable,
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LineStippleParams,
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DepthBiasEnable,
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LogicOpEnable,
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DepthClampEnable,
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@ -144,6 +142,7 @@ void SetupDirtyStateEnable(Tables& tables) {
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setup(OFF(rasterize_enable), RasterizerDiscardEnable);
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setup(OFF(conservative_raster_enable), ConservativeRasterizationMode);
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setup(OFF(line_stipple_enable), LineStippleEnable);
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setup(OFF(line_stipple_params), LineStippleParams);
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setup(OFF(polygon_offset_point_enable), DepthBiasEnable);
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setup(OFF(polygon_offset_line_enable), DepthBiasEnable);
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setup(OFF(polygon_offset_fill_enable), DepthBiasEnable);
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@ -55,6 +55,7 @@ enum : u8 {
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RasterizerDiscardEnable,
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ConservativeRasterizationMode,
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LineStippleEnable,
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LineStippleParams,
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DepthBiasEnable,
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StateEnable,
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LogicOp,
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@ -240,6 +240,7 @@ struct DeviceDispatch : InstanceDispatch {
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PFN_vkCmdSetConservativeRasterizationModeEXT vkCmdSetConservativeRasterizationModeEXT{};
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PFN_vkCmdSetLineRasterizationModeEXT vkCmdSetLineRasterizationModeEXT{};
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PFN_vkCmdSetLineStippleEnableEXT vkCmdSetLineStippleEnableEXT{};
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PFN_vkCmdSetLineStippleEXT vkCmdSetLineStippleEXT{};
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PFN_vkCmdSetDepthBiasEnableEXT vkCmdSetDepthBiasEnableEXT{};
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PFN_vkCmdSetLogicOpEnableEXT vkCmdSetLogicOpEnableEXT{};
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PFN_vkCmdSetDepthClampEnableEXT vkCmdSetDepthClampEnableEXT{};
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@ -1452,6 +1453,11 @@ public:
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dld->vkCmdSetLineStippleEnableEXT(handle, enable ? VK_TRUE : VK_FALSE);
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}
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void SetLineStippleEXT(u32 factor, u16 pattern) const noexcept
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{
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dld->vkCmdSetLineStippleEXT(handle, factor, pattern);
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}
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void SetDepthBiasEnableEXT(bool enable) const noexcept {
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dld->vkCmdSetDepthBiasEnableEXT(handle, enable ? VK_TRUE : VK_FALSE);
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}
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