Commit graph

8 commits

Author SHA1 Message Date
ReinUsesLisp
143db4b112 glasm: Catch more register leaks
Add support for null registers. These are used when an instruction has
no usages.

This comes handy when an instruction is only used for its CC value, with
the caveat of having to invalidate all pseudo-instructions before
defining the instruction itself in the register allocator. This commits
changes this.

Workaround a bug on Nvidia's condition codes conditional execution using
branches.
2021-07-22 21:51:33 -04:00
ReinUsesLisp
c455c92d76 glasm: Do not alias ConditionRef for now
Immediate condition refs where not handled correctly. Just move the
value for now.
2021-07-22 21:51:32 -04:00
ReinUsesLisp
5c6dc51c69 shader: Read branch conditions from an instruction
Fixes the identity removal pass.
2021-07-22 21:51:32 -04:00
ReinUsesLisp
64039f6f4b glasm: Fix aliased bitcasts ref counting 2021-07-22 21:51:31 -04:00
ReinUsesLisp
cbac486530 glasm: Add conversion instructions to GLASM 2021-07-22 21:51:31 -04:00
ReinUsesLisp
fc009ca296 glasm: Initial GLASM fp64 support 2021-07-22 21:51:30 -04:00
ReinUsesLisp
8de3f88656 glasm: Implement GLASM fp16 packing and move bitwise insns 2021-07-22 21:51:30 -04:00
ReinUsesLisp
d9b9c10f32 glasm: Add GLASM backend infrastructure 2021-07-22 21:51:30 -04:00