Commit graph

166 commits

Author SHA1 Message Date
Markus Wick
264030c070 gl_rasterizer: Skip VB upload if the state is clean. 2018-11-17 14:28:54 +01:00
Frederic L
c76f4b6aec global: Use std::optional instead of boost::optional (#1578)
* get rid of boost::optional

* Remove optional references

* Use std::reference_wrapper for optional references

* Fix clang format

* Fix clang format part 2

* Adressed feedback

* Fix clang format and MacOS build
2018-10-30 00:03:25 -04:00
Subv
46b33657b6 GPU: Basic implementation of the Kepler Inline Memory engine (p2mf).
This engine writes data from a FIFO register into the configured address.
2018-09-12 13:57:08 -05:00
Markus Wick
118c1c36c1 video_core: Refactor command_processor.
Inline the WriteReg helper as it is called ~20k times per frame.
2018-09-10 22:06:16 +02:00
Markus Wick
a5613f87ef video_core: Move command buffer loop.
This moves the hot loop into video_core. This refactoring shall reduce the CPU overhead of calling ProcessCommandList.
2018-09-10 22:06:13 +02:00
Markus Wick
ca64dbd6fe command_processor: Use std::array for bound_engines.
subchannel is a 3 bit field. So there must not be more than 8 bound engines.
And using a hashmap for up to 8 values is a bit overpowered.
2018-09-04 14:10:05 +02:00
Hexagon12
d87674e755 Lowered down the logging for methods 2018-08-07 19:51:40 +03:00
James Rowe
d74d2a77cb Update clang format 2018-07-02 21:45:47 -04:00
James Rowe
e159c550d8 Rename logging macro back to LOG_* 2018-07-02 21:45:47 -04:00
Subv
df214db493 GPU: Partially implemented the Maxwell DMA engine.
Only tiled->linear and linear->tiled copies that aren't offsetted are supported for now. Queries are not supported. Swizzled copies are not supported.
2018-06-12 11:27:36 -05:00
Subv
91f05992e4 GPU: Allow command lists to rebind a channel to another engine in the middle of the command list. 2018-05-24 17:32:46 -05:00
Subv
219b5d34e7 GPU: Move the Maxwell3D macro uploading code to the inside of the Maxwell3D processor.
It doesn't belong in the PFIFO handler.
2018-04-25 11:55:27 -05:00
Subv
f42b93399f GPU: Corrected the upper bound of the PFIFO method ids in the command processor. 2018-04-25 11:53:54 -05:00
Lioncash
f5bd2617a8 video-core: Move logging macros over to new fmt-capable ones 2018-04-25 09:13:57 -04:00
bunnei
b6bed8fd74 memory_manager: Make GpuToCpuAddress return an optional. 2018-04-24 17:49:19 -04:00
bunnei
ebef12f037 memory_manager: Use GPUVAdddr, not PAddr, for GPU addresses. 2018-04-24 17:40:43 -04:00
Subv
a8cb6ba213 GPU: Store uploaded GPU macros and keep track of the number of method parameters. 2018-03-18 11:51:46 -05:00
Subv
29c026fae1 GPU: Macros are specific to the Maxwell3D engine, so handle them internally. 2018-03-18 11:51:45 -05:00
Subv
6796e37911 GPU: Process command mode 5 (IncreaseOnce) differently from other commands.
Accumulate all arguments before calling the desired method.

Note: Maybe we should do the same for the NonIncreasing mode?
2018-03-16 20:32:44 -05:00
Subv
0088b3128b Make a GPU class in VideoCore to contain the GPU state.
Also moved the GPU MemoryManager class to video_core since it makes more sense for it to be there.
2018-02-11 23:44:12 -05:00
Subv
35176a0f73 GPU: Added a command processor to decode the GPU pushbuffers and forward the commands to their respective engines. 2018-02-11 22:42:48 -05:00
James Rowe
a5b9cd4d18 Remove references to PICA and rasterizers in video_core 2018-01-12 19:11:03 -07:00
bunnei
2ea8867549 hle: Initial implementation of NX service framework and IPC. 2017-10-14 22:18:42 -04:00
Huw Pascoe
e38656565d Extracted the attribute setup and draw commands into their own functions 2017-10-04 01:08:29 +01:00
James Rowe
a10022da25 Remove pipeline.gpu_mode and fix minor issues 2017-09-23 09:28:20 -06:00
James Rowe
08a1641f8a GPU: Add draw for immediate and batch modes
PR #1461 introduced a regression where some games would change configuration
even while in the poorly named "drawing" mode, which broke the heuristic
citra was using to determine when to draw the batch. This change adds
back in a draw call for batching, and also adds in a draw call in
immediate mode each time it adds a triangle.
2017-09-11 09:21:43 -06:00
wwylele
35b3fef422 pica/command_processor: build geometry pipeline and run geometry shader
The geometry pipeline manages data transfer between VS, GS and primitive assembler. It has known four modes:
 - no GS mode: sends VS output directly to the primitive assembler (what citra currently does)
 - GS mode 0: sends VS output to GS input registers, and sends GS output to primitive assembler
 - GS mode 1: sends VS output to GS uniform registers, and sends GS output to primitive assembler. It also takes an index from the index buffer at the beginning of each primitive for determine the primitive size.
 - GS mode 2: similar to mode 1, but doesn't take the index and uses a fixed primitive size.
hwtest shows that immediate mode also supports GS (at least for mode 0), so the geometry pipeline gets refactored into its own class for supporting both drawing mode.
In the immediate mode, some games don't set the pipeline registers to a valid value until the first attribute input, so a geometry pipeline reset flag is set in `pipeline.vs_default_attributes_setup.index` trigger, and the actual pipeline reconfigure is triggered in the first attribute input.
In the normal drawing mode with index buffer, the vertex cache is a little bit modified to support the geometry pipeline. Instead of OutputVertex, it now holds AttributeBuffer, which is the input to the geometry pipeline. The AttributeBuffer->OutputVertex conversion is done inside the pipeline vertex handler. The actual hardware vertex cache is believed to be implemented in a similar way (because this is the only way that makes sense).
Both geometry pipeline and GS unit rely on states preservation across drawing call, so they are put into the global state. In the future, the other three vertex shader units should be also placed in the global state, and a scheduler should be implemented on top of the four units. Note that the current gs_unit already allows running VS on it in the future.
2017-08-19 10:13:20 +03:00
wwylele
089c0d897b pica: upload shared shader code to both unit 2017-08-07 10:30:05 +03:00
Yuri Kunde Schlesner
85c524bc45 Merge pull request #2697 from wwylele/proctex
Implemented Procedural Texture (Texture Unit 3)
2017-05-24 21:37:42 -07:00
wwylele
b010ff8174 pica/swrasterizer: implement procedural texture 2017-05-20 13:50:50 +03:00
wwylele
c033f16977 pica: use correct register value for shader bool_uniforms
variable value is not masked. the masked and combined register value should be used instead
2017-05-17 22:14:09 +03:00
Jannik Vogel
f3efa5e031 Pica: Write GS registers
This adds the handlers for the geometry shader register writes which will call the functions from the previous commit to update registers for the GS.
2017-05-12 16:22:37 +02:00
Jannik Vogel
52c66441ab Pica: Write shader registers in functions
The commit after this one adds GS register writes, so this moves the VS handlers into functions so they can be re-used and extended more easily.
2017-05-12 16:22:37 +02:00
Yuri Kunde Schlesner
ddf23d4a2e VideoCore: Split regs.h inclusions 2017-02-09 00:04:24 -08:00
Yuri Kunde Schlesner
55110e9361 VideoCore: Use union to index into Regs struct
Also remove some unused members.
2017-02-08 22:13:25 -08:00
Yuri Kunde Schlesner
a0b1957425 VideoCore: Move Regs to its own file 2017-02-04 13:59:12 -08:00
Yuri Kunde Schlesner
90d220d1b3 VideoCore: Split geometry pipeline regs from Regs struct 2017-02-04 13:59:11 -08:00
Yuri Kunde Schlesner
1242f42a09 VideoCore: Split texturing regs from Regs struct 2017-02-04 13:59:09 -08:00
Yuri Kunde Schlesner
d3928b7f9a VideoCore: Split rasterizer regs from Regs struct 2017-02-04 13:08:47 -08:00
Yuri Kunde Schlesner
dcdaff5ecc VideoCore: Split shader output writing from semantic loading 2017-01-29 21:31:37 -08:00
Yuri Kunde Schlesner
067b9b54bd VideoCore: Consistently use shader configuration to load attributes 2017-01-29 21:31:37 -08:00
Yuri Kunde Schlesner
e05770fec4 VideoCore: Use correct register for immediate mode attribute count 2017-01-29 21:31:36 -08:00
Yuri Kunde Schlesner
a4a4b6408c VideoCore: Rename some types to more accurate names 2017-01-29 21:31:36 -08:00
Yuri Kunde Schlesner
07b51a7da0 VideoCore: Change misleading register names
A few registers had names such as "count" or "number" when they actually
contained the maximum (that is, count - 1). This can easily lead to hard
to notice off by one errors.
2017-01-29 21:31:36 -08:00
Yuri Kunde Schlesner
ab0b74b0f3 VideoCore/Shader: Move entry_point to SetupBatch 2017-01-25 18:53:25 -08:00
Yuri Kunde Schlesner
1994f1a6f2 VideoCore/Shader: Move per-batch ShaderEngine state into ShaderSetup 2017-01-25 18:53:25 -08:00
Yuri Kunde Schlesner
c863fc36ce Shader: Remove OutputRegisters struct 2017-01-25 18:53:25 -08:00
Yuri Kunde Schlesner
73e7bc2592 VideoCore/Shader: Split shader uniform state and shader engine
Currently there's only a single dummy implementation, which will be
split in a following commit.
2017-01-25 18:53:23 -08:00
Yuri Kunde Schlesner
03d2b6aa89 VideoCore/Shader: Use only entry_point as ShaderSetup param
This removes all implicit dependency of ShaderState on global PICA
state.
2017-01-25 18:53:23 -08:00
Yuri Kunde Schlesner
2771bde17a VideoCore/Shader: Extract input vertex loading code into function 2017-01-25 18:53:20 -08:00