16 commits

Author	SHA1	Message	Date
ReinUsesLisp	dda21fd317	shader: FMUL, select, RRO, and MUFU fixes	2021-07-22 21:51:22 -04:00
ReinUsesLisp	98bd83997c	shader: Fix MOV(reg), add SHL variants and emit neg and abs instructions	2021-07-22 21:51:22 -04:00
ReinUsesLisp	16a5b4f494	spirv: Fixes and Intel specific workarounds	2021-07-22 21:51:22 -04:00
ReinUsesLisp	e755a13d06	shader: Rename, implement FADD.SAT and P2R (imm)	2021-07-22 21:51:22 -04:00
ReinUsesLisp	6350a277a3	shader: Add denorm flush support	2021-07-22 21:51:22 -04:00
ReinUsesLisp	a2fe90fa60	spirv: Add lower fp16 to fp32 pass	2021-07-22 21:51:22 -04:00
ReinUsesLisp	a5f87011d3	shader: Primitive Vulkan integration	2021-07-22 21:51:22 -04:00
ReinUsesLisp	973936894d	shader: Simplify ISCADD	2021-07-22 21:51:22 -04:00
ReinUsesLisp	76a3a2510f	shader: Misc fixes	2021-07-22 21:51:22 -04:00
ReinUsesLisp	c4d75e4b78	shader: Initial implementation of an AST	2021-07-22 21:51:22 -04:00
ReinUsesLisp	5ee600cf64	spirv: Initial SPIR-V support	2021-07-22 21:51:22 -04:00
ReinUsesLisp	b229ffc0bc	shader: Add pools and rename files	2021-07-22 21:51:21 -04:00
ReinUsesLisp	f5b3324bca	shader: Make typed IR	2021-07-22 21:51:21 -04:00
ReinUsesLisp	f5605b424f	shader: Initial instruction support	2021-07-22 21:51:21 -04:00
ReinUsesLisp	1b576ed4cb	shader: SSA and dominance	2021-07-22 21:51:21 -04:00
ReinUsesLisp	e6892e9da6	shader: Initial recompiler work	2021-07-22 21:51:21 -04:00