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99ceb03a1c
This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
71 lines
2.5 KiB
C++
71 lines
2.5 KiB
C++
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/load_constant.h"
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namespace Shader::Maxwell {
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using namespace LDC;
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namespace {
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std::pair<IR::U32, IR::U32> Slot(IR::IREmitter& ir, Mode mode, const IR::U32& imm_index,
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const IR::U32& reg, const IR::U32& imm_offset) {
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switch (mode) {
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case Mode::Default:
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return {imm_index, ir.IAdd(reg, imm_offset)};
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case Mode::IS: {
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// Segmented addressing mode
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// Ra+imm_offset points into a flat mapping of const buffer
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// address space
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const IR::U32 address{ir.IAdd(reg, imm_offset)};
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const IR::U32 index{ir.BitFieldExtract(address, ir.Imm32(16), ir.Imm32(16))};
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const IR::U32 offset{ir.BitFieldExtract(address, ir.Imm32(0), ir.Imm32(16))};
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return {ir.IAdd(index, imm_index), offset};
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}
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default:
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break;
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}
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throw NotImplementedException("Mode {}", mode);
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}
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} // Anonymous namespace
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void TranslatorVisitor::LDC(u64 insn) {
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const Encoding ldc{insn};
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const IR::U32 imm_index{ir.Imm32(static_cast<u32>(ldc.index))};
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const IR::U32 reg{X(ldc.src_reg)};
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const IR::U32 imm{ir.Imm32(static_cast<s32>(ldc.offset))};
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const auto [index, offset]{Slot(ir, ldc.mode, imm_index, reg, imm)};
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switch (ldc.size) {
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case Size::U8:
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X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 8, false)});
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break;
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case Size::S8:
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X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 8, true)});
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break;
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case Size::U16:
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X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 16, false)});
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break;
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case Size::S16:
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X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 16, true)});
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break;
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case Size::B32:
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X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 32, false)});
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break;
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case Size::B64: {
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if (!IR::IsAligned(ldc.dest_reg, 2)) {
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throw NotImplementedException("Unaligned destination register");
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}
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const IR::Value vector{ir.GetCbuf(index, offset, 64, false)};
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for (int i = 0; i < 2; ++i) {
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X(ldc.dest_reg + i, IR::U32{ir.CompositeExtract(vector, static_cast<size_t>(i))});
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}
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break;
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}
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default:
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throw NotImplementedException("Invalid size {}", ldc.size.Value());
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}
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}
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} // namespace Shader::Maxwell
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